The present invention relates to a semiconductor device and its manufacturing technology, and particularly to a semiconductor device in which a trench gate type MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a p channel is provided with an overheat cutoff circuit, and a technology effective if applied to its manufacture.
A power MISFET with an overheat cutoff circuit built therein has been disclosed in Japanese Unexamined Patent Publication No. Sho 63(1988)-229758 (Patent Document 1). According to a technology described in the patent document 1, a gate resistor is provided between a gate electrode of the power MISFET and an external gate terminal (gate pad). Further, a protection circuit MISFET is provided between the gate electrode of the power MISFET and a source electrode thereof. When the power MISFET is brought to an overheated state, the protection circuit MISFET is turned on to allow current to flow through the gate resistor. Thus, the voltage applied to the gate electrode of the power MISFET is reduced to turn off the power MISFET, thereby preventing device breakdown due to overheating.
A technology for enhancing avalanche capability or breakdown tolerance of a trench gate type power MISFET having an n channel has been disclosed in Japanese Unexamined Patent Publication No. 2005-57049 (Patent Document 2). Described specifically, a p+-type semiconductor region is formed at the bottom of a contact trench or groove of the trench gate type power MISFET. A p-type semiconductor region, which contacts the p+-type semiconductor region and an n−-type monocrystalline silicon layer and is lower in impurity concentration than the p+-type semiconductor region, is formed below the p+-type semiconductor region. Further, an n-type semiconductor region, which contacts the p-type semiconductor region and is higher in impurity concentration than the n−-type monocrystalline silicon layer, is formed in the n−-type monocrystalline silicon layer below the p-type semiconductor region.